1. Field of the Invention
This invention relates to error detection in logic circuits and, more particularly, to detecting errors in dynamic logic circuits.
2. Description of the Related Arts
Domino circuits have become popular in the design of high performance adders because they offer fast switching speeds and reduced areas. The use of conventional domino logic, however, introduces many design risks because it is very sensitive to circuit and to layout topologies and prone to circuit failures. This makes the detection and debugging of circuit failures difficult. Although simulation tests may be useful for debugging circuit behavior or logic, some problems that affect real-world circuit functionality, such as electrical coupling, often occur due to the particular circuit or layout topology used for the integrated circuit silicon implementation. Thus, a circuit may perform properly in simulation, but fail when implemented as an integrated circuit.
Dynamic logic circuits rely upon the storage of charge. Domino logic circuit design techniques are a well-known type of dynamic logic. In domino logic, there are generally two clocking operations: a precharge phase and an evaluation phase. During the precharge phase, the dynamic node is charged to VDD (positive supply voltage, logic “high” or logic “1” value). In the evaluation phase, a combinational logic function is evaluated, and the dynamic node is conditionally discharged to VSS (negative supply voltage or ground).
For a given set of inputs, if the function evaluates “true,” then a path to VSS exists to discharge the dynamic node, thereby causing the static output inverter to drive the gate output to logic “1.” For example, a 2-input AND gate outputs logic “1” when both inputs A and B are “true.” That is, the function evaluates “true” when both A and B are logic “1” during the evaluation phase. If both A and B are not logic “1” during the evaluation phase, no path to VSS is created and the dynamic node has to maintain its stored state, which holds the gate output at logic “0.”
In domino logic gates, one mode of circuit failure occurs when the dynamic node cannot be discharged to VSS as is required for proper gate evaluation. This type of failure, however, does not occur during normal operation of an integrated circuit that includes domino gates. Other tests performed on the integrated circuit reveal this problem before the integrated circuit is placed into normal operation, and faulty parts are appropriately sorted out. Another possible mode of circuit failure occurs when the dynamic node is not held at a logic “1” value. These failures occur for a variety of reasons, for example, charge sharing, noise on the input signals, or noise on the power rails can corrupt the state stored on the dynamic node. A charge sharing problem occurs when the charge that is stored at the dynamic node in the precharge phase is shared among the junction capacitance of transistors in the evaluation phase. Charge sharing may degrade the output voltage level and cause an erroneous output value. During the evaluation phase, the dynamic node cannot be recharged, and therefore the output stays at the erroneous value. In a functional unit such as an adder, misevaluation of a single gate can cause an error in the arithmetic result. See, e.g., Pranjal Srivastava, Andrew Pua, and Larry Welch, “Issues in the Design of Domino Logic Circuits,” 8th GLS-VLSI, pp. 108-112, 1998 for further details of domino circuit failures.
Conventional techniques for detecting circuit errors include duplicating functional units and comparing the result of each functional unit. Figure (“FIG.”) 1 is block diagram of a prior art functional unit error detection system and technique. This system includes a first adder 110, a second adder 120, and a comparator 130. The adders 110, 120 couple with the comparator 130. The comparator produces a functional unit error signal 140. As illustrated, the first adder 110 computes the addition of signals A and B, and the second adder 120 also computes the addition of signals A and B. The result of the first adder 110 and the result of the second adder 120 are compared by the comparator 130 to determine the functional unit error 140. That is, if the first adder 110 produces a different result from the second adder 120, then a circuit error has occurred with either the first adder 110 or the second adder 120.
Although duplicating functional units provides some additional integrity in the result, one problem with using duplicate functional units to detect errors is that some errors could be aliased. While transient errors (i.e., soft errors) can be detected with re-computation techniques, aliasing can cause duplicate functional units to produce an incorrect, but identical result. Such identically incorrect results would be undetected by the comparator 130. Therefore, including duplicated functional units does not necessarily provide absolute integrity or guaranteed validity in the result. Circuit design issues, layout issues, or electrical issues, such as coupling, contribute to this problem.
Another problem with using duplicate functional units to detect errors is the granularity of the error detection result. Detecting an error at the functional unit level does not provide much information to the circuit designer for debugging the error within the particular functional unit. The circuit designer does not know, for example, which circuits of the adder contributed to the erroneous result. Therefore, eliminating the errors is a difficult and time-consuming process.
A further problem with detecting errors in duplicate functional units is the additional hardware required. The area used by additional functional units and result comparators increases the integrated circuit chip footprint that could be allocated to other system functions. Moreover, the additional hardware increases heat generation that may cause circuit failures or require the use of more expensive cooling strategies. Conventional error detection techniques can alias the problems that occur in all the functional units, leaving the problem undetected. Further, in a conventional approach, if an error does get detected, debugging the circuit is often a long and tedious process because of the granularity of the error detection determination.
What is therefore needed is an apparatus and a method to detect reliably errors in domino logic circuits.